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Jeff Law 900b5386f5 [RISC-V] Improve SI->DI zero/sign extension patterns for RISC-V
--  From the original submission in Oct 2025 --

So this is a slightly scaled back variant of a patch I've been working
on.  I'd originally planned to handle both zero and sign extensions, but
there's some fallout with the sign extension adjustments that I'm going
to need more time to tackle.  This piece stands on its own and unlocks a
subsequent patch to improve codegen.  No sense in having it possibly
miss the merge window.

This patch adjusts the core zero-extension patterns as well as one
closely related combiner pattern.

For the named expanders, we now generate shift pairs if the Zba/Zbb
extensions are not available and the source operand is a REG.  Things
are kept as-is for MEMs.

The existing define_insn_and_split it turned into a define_insn that
only handles MEM sources.  Those instructions are always available, so
no need to mess with shift pairs.  This avoids regressions with a
follow-up patch which enhances a closely related combiner pattern.

That closely related combiner pattern is a define_insn_and_split which
can now turn into a simpler define_split.  So that's adjusted as well.

The net is we drop 3 define_insn_and_splits and occasionally get better
code as a result.  It also makes it possible to improve some additional
cases which I'll handle as a followup.

The test changes are minimal and mostly related to making sure we have
the right Zb* things enabled based on what the test relies on under the
hood.  It's not even clear that part of the change is strictly necessary
anymore.  I see it more as test hygiene than anything.

This has been bootstrapped and regression tested on the Pioneer which is
a good test since it doesn't have any of the Zb* extensions and thus
relies heavily on the shift-pair approach to zero extensions.
riscv32-elf and riscv64-elf have also been regression tested.  The BPI
hasn't started chewing on this patch yet.

--

Subsequent changes were to the testsuite to ensure that --with-cpu or
--with-tune configure time options wouldn't impact the testresults.

gcc/

	* config/riscv/riscv.cc (riscv_rtx_costs): Properly cost pack insns
	for Zbkb.
	* config/riscv/riscv.md (zero_extendsidi2): Expand into shift pairs
	when the appropriate instructions are not available.
	(zero_extendhi<GPR:mode>2): Simlarly.
	(*zero_extendsidi2_internal): Make a simple define_insn.  Only handle
	MEM sources.
	(*zero_extendhi<GPR2:mode>2): Similarly.
	(zero_extendsidi2_shifted): Turn into a define_split and generalize
	to handle more constants.
	* config/riscv/predicates.md (dimode_shift_operand): New predicate.

gcc/testsuite/

	* gcc.target/riscv/slt-1.c: Skip for -Oz as well.  Set explicit branch
	cost.
	* gcc.target/riscv/zba-shNadd-04.c: Add Zbb to command line switches.
	* gcc.target/riscv/zba-slliuw.c: Add Zbs to command line switches.
	* gcc.target/riscv/zbs-zext.c: Add Zbs to command line switches.
	* gcc.target/riscv/shift-shift-6.c: New test.
	* gcc.target/riscv/shift-shift-7.c: New test.
	* gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: Accept lh or lhu.
	* gcc.target/riscv/amo/a-ztso-load-relaxed.c: Accept lh or lhu.
	* gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c: Accept lh or lhu.
	* gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c: Accept lh or lhu.
	* gcc.target/riscv/pr105314.c: Set explicitly branch cost.
	* gcc.target/riscv/pr105314-rtl.c: Set explicitly branch cost.
2026-05-18 15:33:21 -06:00
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MAINTAINERS MAINTAINERS: Add myself to write after approval and DCO. 2026-05-13 13:18:07 +00:00
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